For various reasons, there has recently been increased interest in fast photodetectors produced using complementary-metal-oxide semiconductor (CMOS) technology. First, CMOS circuitry is generally less expensive than other technologies, such as Gallium Arsenide or bipolar silicon technologies. Further, CMOS circuitry generally dissipates less power than other technologies. Additionally, CMOS photodetectors can be formed on the same substrate as other low power CMOS devices, such as metal-oxide semiconductor field effect transistors (MOSFETs).
However, despite the potential advantages, there are various reasons why conventional CMOS technology has not been optimal for producing a fast photodetector. More specifically, photodetectors produced using CMOS technology have proven to be much slower than photodetectors produced using other technologies, such as bipolar silicon technology. The slower the photodetector, the lower the bandwidth of information that can be detected using the photodetector.
In a CMOS photodetector, photo-generated electron-hole pairs in the depletion region are collected quickly through carrier drift process due to the presence of strong electric field. On the other hand, carriers generated in the neutral zone of the substrate migrate by diffusion. The diffusion-based component has a much slower time-response than the field-aided drift counterpart. FIG. 1 illustrates the typical transient behavior of the photocurrent for carrier drift and diffusion. Accordingly, the output signal of the photodetector can be characterized by a fast time-constant τfast and a slow time-constant τslow representing carrier drift and diffusion respectively. In addition, Afast and Aslow are the percentage contributions from carrier drift and carrier diffusion respectively. The summation of Afast and Aslow is equal to 1.
To achieve high-speed operations, Aslow should be kept to a minimum, normally less than 1% of the total amplitude. Otherwise, the transient response of photocurrent exhibits the so-called slow tail phenomena.
Several schemes have been suggested to minimize the slow tail effect in silicon technologies. In one scheme, a buried collector layer is used to screen out the slow diffusive carriers in bipolar or BiCMOS technologies. However, this topology results in responsivity that is typically low. It presents the most common tradeoff, that of responsivity for speed. In another scheme, a very thick and lowly-doped substrate is used with a large reverse bias voltage in nonstandard CMOS technology. However, this topology requires extra custom processing steps. In pure CMOS technology, a spatially modulated detector is the only scheme reported so far to achieve slow tail compensation. However, this approach suffers from a low responsivity since a substantial detector area is blocked to generate the slow diffusive component. Accordingly, there is still a need to provide an effective solution to compensate for slow diffusive carriers generated in a conventional CMOS photodetector.